In conventional memory buffers, such as DDR3-compatible memory buffers, write and read commands may be spaced a minimum of four cycles apart while the data associated with these commands may be delayed as many as 40 cycles. The command and accompanying control data such as burst length and training parameters must therefore be delayed a corresponding amount of time. One conventional technique to delay command and control data is to use respective pipelines for the signals being delayed. Unfortunately, the use of such pipelines to control the timing of a relatively large number of signals may require an excessive amount of layout area to implement and may not efficiently support variable timing that may be command specific. Moreover, in some memory buffer designs, relatively slower signals are frequently generated in response to relatively faster signals, which can be a problem when the timing of the relatively faster signals is changed. Accordingly, it would be advantageous to provide a greater degree of independent control between signals having different timing requirements. Moreover, on the DDR-compatible memory buffer, register-transfer level (RTL) circuitry controls custom logic operating at the same frequency but at varying clock phases and must pass control information with minimum latency so that low read and write latencies of the DDR3 specification can be supported.